Trends in microelectronic devices are toward increasing miniaturization, circuit density, operating speeds and switching rates. These trends have directly impacted the complexity associated with the design and manufacture of microelectronic dice, microelectronic devices, which include the microelectronic die and a substrate, microelectronic packages, as well as computing devices in general. Examples of computing devices include, but are not limited to servers, personal computers and “special” purpose computing devices. Personal computers may have form factors, such as desktop, laptop, tablet, and the like. “Special” purpose computing devices may include set top boxes, personal digital assistants, wireless phones, and the like.
In particular, attention has increasingly shifted to microelectronic packaging as a means to meet the demands for enhanced system performance. As shown in FIG. 4, current microelectronic packages typically consist of a microelectronic die 50 electrically interconnected to a carrier substrate 52, which are commonly encapsulated with an encapsulation material 54, such as molded plastic, epoxy or other suitable materials. Additional components, including but not limited to a heat dissipation device, may be included as part of the microelectronic package.
As demand increases, it has become necessary to use multiple dice that work in conjunction with one another. When using multiple dice, however, it becomes critical to position the dice close together since excessive signal transmission distance deteriorates signal integrity and propagation times. The use of conventional single-die microelectronic packages, however, is not commensurate with the need to shorten signal transmission distance because they typically have an area (or footprint) many times larger than the area of the die. This not only increases transmission distances, but it also decreases packaging density.
One solution to create higher density packaging, reduce area requirements and shorten signal transmission distances has been to vertically stack and electrically interconnect multiple dice in a single microelectronic package. Another solution has been to stack multiple microelectronic packages, such as ball grid arrays (BGA) and chip scale packages (CSP) in an array. Although these stacked microelectronic packages provide certain advantages, further size reduction and performance enhancement has been difficult to obtain due to the physical dimension, design and manufacturing constraints of the individual microelectronic packages and the interconnection to the other microelectronic packages in the array.
FIG. 5 shows one assembly known in the art wherein multiple single-die microelectronic packages, as shown and described in FIG. 4 are stacked in an array. Each carrier substrate 52 has multiple conductive land pads 56 at the die side 60 of the carrier substrate 52 that are electrically interconnected to conductive traces (not shown) within the carrier substrate 52. Land pads 56 include but are not limited to conductive pads, through holes, vias, and any other structure adapted for electrical interconnection. When stacked, the land pads 56 are positioned for electrical communication with respective bond pads 56′ on the non-die side 62 of carrier substrate 52 of the adjacent microelectronic package. An interconnect 58, such as solder, is used to electrically interconnect the land pads 56 of one microelectronic package to the bond pads 56′ of another microelectronic package.
A number of problems exist with stacking prior art microelectronic packages. One, it limits package-to-package interconnect scalability, which involves varying the interconnect pitch (distance between center points of the conductive pads) without changing the gap in between packages. For a fine pitch interconnect, the conductive interconnect 58 must be decreased so as not to bridge with adjacent interconnects. However, it is important to keep appropriate standoff distance from one microelectronic package to another in order to accommodate the die, encapsulation material, and other components, if used. To maintain this standoff distance, the interconnect 58 must be of a sufficient quantity, which limits decreasing the pitch. Decreasing the pitch, however is necessary to keep up with the advancements in microelectronic packages, as more input/output signal leads and power leads are required.
Another problem with stacking microelectronic packages is that the package carrier substrate 52, especially the carrier substrate at the bottom of the stack, commonly is subjected to increased stress and flexing. The flexing of the carrier substrate is undesirable because it tends to result in open connections, reduces the microelectronic package effectiveness, and leads to microelectronic package failure.